1. Field of the Invention
The present invention relates to electronic circuits, and more specifically to a device for generating a high voltage using a charge pump.
2. Description of Related Art
Non-volatile memories of the EEPROM and Flash EPROM type use a high voltage for their programming. This high voltage is generally in the range of 10 to 20 volts. In an integrated circuit, this high voltage is produced from the supply voltage of the integrated circuit using a high voltage generation device having a charge pump device. The high voltage generation device also includes a device for regulating the output voltage level to obtain a level that is determined as a function of the application.
The regulation can be done by a clamping device located at the output of the charge pump device. However, such a clamping device has a few drawbacks. First, a great deal of energy is lost due to the power dissipated by the clamping device. The clamping device must also be capable of supporting a dissipation of this kind (i.e., it must be sufficiently sized, and therefore fairly costly). Furthermore, since clamping is involved, the charge pump works all of the time. This results in an additional loss of energy.
Another conventional regulation device consists of a circuit for comparing the voltage level at the output of the charge pump device with the level of a reference voltage. If the output level is higher than the reference level, the charge pump is stopped. This type of regulation of the charge pump device is called the "go-no-go" mode of regulation. The major advantage of this type of comparator-based regulation is the high efficiency of the charge pump device, which arises out of the fact that it does not work all of the time.
When the high voltage is not being used, it is reactivated from time to time to maintain the output level at the reference level. It is also reactivated when the programming voltage is used, to maintain the output level despite the load that is then applied to it (i.e., for the programming of memory cells). The energy consumption is therefore near the optimum. However, with such regulation, the level obtained at the output of the charge pump device is not perfectly stable. More specifically, the output level oscillates around the reference value as will now be explained with reference to the conventional device for generating a high voltage shown in FIG. 1.
The high voltage generation device includes an oscillator 10 that outputs two clock signals .PHI.0 and /.PHI.0 in phase opposition that are used by a charge pump device 20. This charge pump device 20 outputs a high voltage HV. This high voltage is used, for example, by circuitry 40 for programming or erasing a non-volatile memory. This high voltage HV is also supplied to a regulation device 30 that outputs a control signal Run. This control signal Run is supplied to an enabling input En of the oscillator.
FIG. 2 shows an embodiment of such a high voltage regulation device. A typical oscillator consists of a loop of an odd number of inverters. The oscillator 10 of FIG. 2 conventionally has a stage for generating a clock signal .PHI.i that includes, in the illustrated embodiment, an inverter 11 followed in series by a resistor 12 and a
Schmitt trigger 13. At the input of the Schmitt trigger 13, there is provided a capacitor 14 that is also connected to ground. The output S1 of the Schmitt trigger is looped to the input E1 of the inverter 11 through a NAND-type logic gate 15.
At another input, this logic gate receives the control signal Run that is supplied to the enabling input En of the oscillator. The input E1 of the inverter 11 gives the clock signal .PHI.i. This clock signal is supplied to the input of an output stage that delivers the two clock signals .PHI.0 and /.PHI.0 in phase opposition to the charge pump device 20. The clock signal .PHI.i is supplied to a first inverter 16 followed in series by a second inverter 17. In the illustrated embodiment, the output of the first inverter 16 delivers the clock signal /.PHI.0 and the output of the second inverter 17 delivers the clock signal .PHI.0.
The charge pump device in the illustrated embodiment is a Schenkel-type multiplier having n+1 series-connected diodes D0 to Dn, with the first diode having its anode connected to Vcc and the last diode giving the high voltage HV for output. An output capacitor Cout is provided between the high voltage output HV and ground. The multiplier also has n capacitors C1 to Cn that are controlled by the clock signals .PHI.0 and /.PHI.0. Each capacitor has a first terminal connected between two successive diodes and a second terminal connected to one of the clock signals. In the illustrated embodiment, the capacitors C1, C3, . . . Cn have their terminals connected to the clock signal .PHI.0 while the capacitors C2, . . . Cn-1 have their terminals connected to the clock signal in phase opposition /.PHI.0. This charge transfer or charge-coupled device is very widely used.
In the illustrated embodiment, the regulation device 30 includes a Zener diode 31 and a resistor 32 series-connected between the high voltage output HV of the charge pump device 20 and ground. An inverter 33, whose input is connected to a connection point 34 (i.e., the midpoint of the arm of the regulation device) between the diode 31 and the resistor 32, outputs the control signal Run. The diode 31 has a
Zener voltage illustratively equal to 18 volts. It is this Zener voltage which gives the reference voltage level Ref for the regulation device.
When the high voltage HV exceeds this reference level of 18 volts, the current in the diode increases and the voltage at the midpoint tends to rise (i.e., because the voltage at the terminals of the Zener diode remains constant). At the output of the inverter 33 of the regulation device 30, the signal Run therefore goes to 0. This deactivates the oscillator 10. When the high voltage HV is lower than the reference level, the current in the arm of the regulation device is very low and the voltage at the midpoint 34 is close to zero. The signal Run then goes to 1. This activates the oscillator.
The signals in such a device for generating a high voltage are shown in FIG. 3. This figure shows the progress as a function of time of the clock signals .PHI.0 and /.PHI.0, the control signal Run, and the high voltage signal HV at the output of the charge pump device, starting from the powering on of the high voltage generation device. As shown, there is a gradual build-up of the output level HV of the charge pump device until the crossing of the reference level Ref of the regulation device. So long as the high voltage has not reached the reference level Ref, the control signal Run remains at 1. Thus, the oscillator remains active and outputs the clock signals .PHI.0 and /.PHI.0.
When the output level HV crosses the reference level Ref, the regulation device detects this and deactivates the oscillator (i.e., through control signal Run). As shown in FIG. 3, this deactivation corresponds to the freezing of the clock signals .PHI.0 and /.PHI.0, which remain in a given state. For the illustrated embodiment, FIG. 3 shows that at the first occurrence where the signal Run goes to zero, .PHI.0 remains at the high level and /.PHI.0 remains at the zero level. The charge pump device therefore no longer operates. The level of the output voltage HV will then gradually fall, either because of current leakages or because of the activation of a circuit for programming the memory (i.e., a load).
The output voltage level will therefore go back to below the reference level Ref. The oscillator is then reactivated, and the output level of the charge pump device will rise again. Thus, when the regulation device has determined that the level of the high voltage HV is greater than the reference level, the oscillator is deactivated. However, this deactivation occurs only after the reaction time of the regulation circuit. It is quite possible during this period of time to have had a trailing edge and/or a leading edge on the clock signals .PHI.0 and /.PHI.0. Since the pulses of these clock signals are square-wave pulses (i.e., since they have very steep edges), the amplitude variation on these clock signals is instantaneous.
Furthermore, the clock signals are only frozen by the deactivation of the oscillator (i.e., they each remain at a high level or at a low level). The transfer of charges to the charge pump device is therefore not immediately stopped. The output voltage therefore continues to rise for a certain time, and crosses the reference level. This results in the oscillation of the amplitude of the level of the output voltage. Since the stopping of the pump is not immediate, the distance from the reference value becomes slightly greater.
To reduce this oscillation, bringing the phase signals to zero does not suffice to prevent a transfer of charges during the reaction time of the regulation device. As described above, since the leading edges of the (square-wave) pulses of the clock signals are very steep, when the level HV at the output of the charge pump device reaches the reference level Ref, the phase signals reach their maximum amplitude before the regulation device has been able to react. Thus, even if the phase signals are then brought to zero, the charge transfer will have continued during the reaction time of the regulation device, and the output level will have greatly exceeded the reference level.